This application is related to Japanese application No. 2001-012035 filed on Jan. 19, 2001, whose priority is claimed under 35 USC xc2xa7 119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including a silicide film on a surface of a semiconductor substrate and the semiconductor device manufactured by the method.
2. Description of the Related Art
In a recent semiconductor device, the performance of the device and the degree of integration are remarkably improved by the advance in minuteness of an element. Especially, in a high speed device to which a minute design rule of 0.35 xcexcm or less gate length is applied, it is necessary to lower parasitic resistance of a diffusion layer which is formed on the surface of a semiconductor substrate as a source/drain region of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Therefore, the surface of the diffusion layer is converted into silicide layer using a SALICIDE (Self Aligned Silicide) process. The SALICIDE process is a technique in which in general, a surface of a diffusion layer formed in a silicon substrate and a surface of a gate electrode are silicidized (converted into, for example, a metal compound comprising titanium and silicon) in a self aligned manner, so that the parasitic resistance of the diffusion layer as well as the contact resistance between a wiring layer formed on an interlayer insulating film and the diffusion layer are lowered.
When a scale-down of a gate is advanced and a gate length becomes short by the improvement in minuteness of an element, a junction depth of the diffusion layer is relatively increased to the gate length. As a result, a leak current in a lateral direction (between source and drain) is increased by a short channel effect, which causes deterioration of element characteristics. Accordingly, in the case where the gate length is made short, it is necessary to make the junction depth shallow. Under such circumstances, when the surface of the diffusion layer is converted into a silicide layer, it is necessary to form a silicide layer to be as thin as possible. That is, if the silicide layer is not made sufficiently thin relatively to the junction depth, the silicide layer itself becomes a factor to cause a leak current in the vertical direction by, for example, diffusion of metal atoms at the time of the reaction of conversion into the silicide layer. However, in the conventional minute design rule of 0.35 xcexcm or 0.25 xcexcm gate length, in the case where a thin silicide layer made of a titanium film is formed, a thin line effect (as line width becomes thin, sheet resistance becomes large) becomes remarkable, and the effect of using the SALICIDE technique disappears.
To this problem, in the minute design rule of 0.18 xcexcm or less gate length, a technique using cobalt (Co) silicide layer having no thin line effect has been reviewed.
However, in the case where cobalt is used as a material of the silicide layer, differently from titanium, since cobalt does not have a reducing property to a native oxide film of the surface of a silicon substrate, there is a problem that a portion where the native oxide film exists is not silicidized, which results disadvantageously in the formation of a spotted silicide layer.
To this problem, Japanese Patent Unexamined Publication No. Hei 10(1998)-98012 proposes a method in which a titanium film is formed under a cobalt film. Hereinafter, this method will be described with reference to FIGS. 3A to 3D.
First, as shown in FIG. 3A, a field insulating film 112 for element isolation is selectively formed on a silicon substrate 111 by a normal LOCOS (Local Oxidation of Silicon) process for defining a MOSFET formation region. A gate electrode 114 made of polycrystalline silicon is formed in the MOSFET formation region through a gate insulating film 113. A low concentration impurity diffusion layer is formed by ion implanting an impurity into an active region (a region of a surface layer of the silicon substrate 111 which becomes source and drain regions) in order to form an LDD (Lightly Doped Drain) structure, and then a side wall 115 is formed on a side surface of the gate electrode 114, and further, an impurity is selectively ion-implanted into the low concentration impurity diffusion layer to form a high concentration impurity diffusion layer as a source region 116 and a drain region 117. In this time, a native oxide film (SiO2) 118 are already formed on the surfaces of the source region 116, the drain region 117 and the gate electrode 114.
Next, the substrate is washed to remove the native oxide films 118 formed on the surfaces of the source region 116, the drain region 117, and the gate electrode 114. Incidentally, although the native oxide films 118 become thin by this washing, they are not actually completely removed and remain, or there is also a case where a native oxide film is again formed after the washing.
As shown in FIG. 3B, a thin titanium film 120 is formed on the whole surface of the silicon substrate in order to reduce the native oxide film, and subsequently, a cobalt film 121 for formation of silicide is formed.
Next, as shown in FIG. 3C, a RTA (Rapid Thermal Annealing) treatment is carried out, so that silicon in the surface of the gate electrode 114, the source region 116 and the drain region 117 is made to react with the cobalt film 121, so that silicide films 122 are formed.
As shown in FIG. 3D, the unreacted titanium film 120 and the unreacted cobalt film 121 on the field insulating film 112 and the side wall 115 are removed by selective etching, a second RTA treatment is further carried out in order to lower the resistance of the silicide films 122. By this, a MOSFET is formed, in which the silicide films 122 are formed in a self aligned manner only on the gate electrode 114, the source region 116 and the drain region 117.
However, in the above method, it is necessary to control the under titanium film to be thin so that the main ingredient in the silicide film becomes cobalt in order to obtain the thin and uniform silicide film having no thin line effect, but it is difficult to form such a thin film with good control and not suitable for further advancement in minuteness of the element.
Generally, a cobalt silicide film is formed to have a thickness about 3.5 times as thick as a cobalt film, and a titanium silicide film is formed to have a thickness about 2.4 times as thick as a titanium film. Thus, in order to suppress the thin line effect, it is necessary that the thickness of the titanium silicide film is controlled to be about 20 percent of the thickness of the cobalt silicide film. Accordingly, for example, if the thickness of the cobalt film is 5 nm, the thickness of the cobalt silicide film becomes about 17.5 nm, and in this case, in order to make the thickness of the titanium silicide film about 20 percent (about 3.5 nm) of the cobalt silicide film, the thickness of the titanium film is made as thin as about 1.4 nm.
Besides, since the titanium film is apt to react with oxygen, the thinner the titanium film is made, the greater the influence of an atmosphere becomes, and there is a problem that the reducing property to the native oxide film can not be expected by the influence of oxidation from the surface side of the substrate.
The present invention provides a method of manufacturing a semiconductor device comprising steps of:
forming a first metal film having a reducing property on a semiconductor substrate;
thermal treating the resulting semiconductor substrate for reducing a native oxide film naturally formed on the semiconductor substrate and for forming a first silicide film on the semiconductor substrate;
removing an unreacted first metal film selectively;
forming a second metal film on the semiconductor substrate; and
thermal treating the resulting semiconductor substrate for forming a second silicide film on a surface of the semiconductor substrate which includes a region where the first silicide film is formed.
Further, according to the present invention, there is provided a semiconductor device manufactured by the above described method.